Semiconductors & Chips

China's semiconductor self-sufficiency drive is broadening from design into foundry and equipment, and the freshest evidence leaves that judgment intact: the binding constraint is still leading-edge lithography, but everything beneath it is being filled in at a faster pace than a designer-only reading would suggest. The new document set adds adjacent supply-chain signals rather than a new central policy, so the story remains one of provincial initiative, corporate execution, and a costly AI boom.

The design track's flagship marker is still Xiaomi's Aug 24 Xuanjie event. The O3 SoC (133 mm², 24B transistors, 5,228,014 AnTuTu) is in mass production and ships in September with the Xiaomi 18 Fold and Pad 9 Pro Max; the O100 AI accelerator (6nm, 3D wafer stacking, 1.22 TB/s) and D100 AD chip are validated for commercial launch next year ¹. The decisive detail is that CXMT is the core LPDDR6 partner, making O3 the world's first flagship SoC with LPDDR6 and the first domestic LPDDR6 in a flagship ². That closes the memory dependency on the design track, but the logic die is still likely TSMC 3nm, keeping the leading-edge foundry link external.

Foundry results give the broadening thesis hard numbers. SMIC's Q2 sales broke $3B (up 36.1% YoY, 20% QoQ, gross margin 25.3%, net profit +261.7% YoY); Hua Hong set a revenue record of $717.5M, ran at 102.8% utilization, and saw profit up 386% ³. Both guided Q3 higher. The composition matters: China-region revenue is 90.2% at SMIC and 78.6% at Hua Hong, with consumer electronics the largest end-market — evidence that AI demand is spilling into mature-node fabs, not that domestic leading-edge logic has advanced.

On equipment, Tuojing Technology topped out its Shenyang base on Aug 10: a near-18-billion-yuan project with planned capacity of 1,000+ thin-film deposition tools per year (PECVD, SACVD, HDPCVD), after deployment across roughly 100 domestic chip lines and ~600M processed wafers ⁴. This is industrial scale-up in deposition, not a lithography breakthrough; EUV/DUV remains the bottleneck. Policy continues to move at provincial level: Jiangsu's Aug 4 "6+6" IC meeting, chaired by Governor Liu Xiaotao, called for support of basic materials, core devices, advanced processes and talent, with province-city-county coordination ⁵. No national chip law or central directive has surfaced.

The cost environment is tightening on two sides. SK Hynix reported DRAM ASPs up ~65% QoQ in Q1 and ~30% in Q2, with NAND up ~75% and ~55%; Huawei's Yu Chengdong warns broad phone price rises are likely ⁶. Nvidia AI-chip prices are reportedly set to rise ~17% ⁷, and PCB leader WUS reported H1 profit +73.7% on AI demand, with 32-layer-plus PCB shipments up 190.8% ⁸. At the same time, Tianfu Communication's Q2 recovery still runs into an upstream optical-chip bottleneck ⁹, and US memory stocks sold off sharply on Aug 24 after Nvidia's seventh straight down session ¹⁰.

That last cluster is the useful counter-signal. China's self-sufficiency push is running through a global AI cycle that is simultaneously raising prices for every link in the chain and wobbling in equity markets. For self-reliant products like Xiaomi's, the same AI boom that lifts domestic fabs and PCB makers also raises the bill of materials; the profits accumulating at SMIC and Hua Hong have not yet been shown to translate into leading-edge capex. The gap below the ceiling is closing, but the ceiling itself is untouched.

Watch SMIC's Q3 earnings and capex guidance, CXMT LPDDR6 supply beyond Xiaomi, Tuojing qualification announcements, and any follow-up documents from Jiangsu's meeting. With no central policy shift, the summary stays the same: China's chip story is now design-plus-foundry-plus-equipment, moving at different speeds but in the same direction.