Semiconductors & Chips

China's semiconductor push is no longer just a design story; it is becoming a memory-integration story. Xiaomi's Aug 24 Xuanjie launch showed three in-house chips, and the new detail that Changxin Storage (CXMT) is the core LPDDR6 partner for the flagship Xuanjie O3 makes this the first time a domestic memory chip rides inside a mainland-designed flagship SoC. That narrows the foreign dependency map on the design track, while the foundry node itself — 3nm, almost certainly TSMC — remains the hard external limit.

The Xuanjie event: O3 is a 133 mm² die with 24 billion transistors and an AnTuTu score of 5,228,014 (industry first to exceed 5 million), in mass production and shipping in September with the Xiaomi 18 Fold and Pad 9 Pro Max. O100 is a 6nm high-bandwidth AI accelerator using 3D wafer-level stacking, 1.22 TB/s bandwidth, near-memory compute, and 330 tokens/s on Xiaomi MiMo 3B; D100 is the AD chip; both completed validation and go commercial next year ^1,2.

The memory angle matters because the prior assumption was that domestic design still depended on foreign memory for flagship performance. O3 is the world's first flagship SoC supporting LPDDR6, and CXMT supplies that memory — the first time domestic LPDDR6 has been used on a flagship processor, putting Chinese low-power memory in the global first tier. This supplements Xiaomi's design self-reliance with a homegrown memory component, even though the logic die still comes from a foreign foundry ².

The state track remains unchanged: no new national-level chip law or central directive surfaced. Hubei's Aug 22 "Plane Tree Plan" meeting had Party Secretary Guan Zhi'ou with YMTC/Changcun Holdings, AMEC, Hwatsing, Skyverse, Kema, Zhenbao plus three new names, and Liaoning's atomic-level manufacturing alliance lists chips among targets. State and industrial capital still dominate hard-tech funding. This reinforces the existing judgment that Beijing relies on provincial clusters and industrial capital, not a single central plan ^3,4.

Market prices in the bottlenecks. STAR/ChiNext 50 is up 23% YTD, semiconductors >70% weight, but the rebound lagged after July's 30% drawdown. Zhongji Innolight's H1 net profit jumped 241.7% yet its stock fell 7.72% post-earnings on cash-flow and customer-concentration worries. Glass-substrate packaging is stuck in reliability qualification — Intel-Lens cooperation advanced, while Samsung Electro-Mechanics' GlaSSEM may slip to 2028+ — and Tianfu Communication's optical-chip bottleneck persists with only 33-36% of consensus profit in H1 ^5,6,7,8.

The competitive frame: Qualcomm's Snapdragon 8 Elite Gen6 and Gen6 Pro, both TSMC 2nm, launch Sep 22; the Pro scores about 4.83 million AnTuTu and has about a one-month exclusivity on the Xiaomi 18 Pro. Xiaomi will thus sell a phone with its own 3nm chip in September while its premium line uses a 2nm Qualcomm part — the structural position of the Chinese semiconductor industry in one image: design competes at the top tier, foundry lead remains external ⁹.

Watch items: whether O100 and D100 move into Xiaomi vehicles next year; whether CXMT LPDDR6 supply expands to other domestic flagships; whether glass-substrate certifications land in 2026 or slip to 2028; whether Hubei cluster adds upstream materials players. The design-track breakout is now broadened by memory integration, but fabrication dependence and reliability qualification remain the gating factors.